Intelligent Machines

Assembling Nanotubes

A one-step method sorts and aligns carbon nanotubes for use in electronics.

A new method for sorting single-walled carbon nanotubes by electronic type and arranging them over a large area could be useful for manufacturing high-performance displays and other electronic devices. Researcher from Stanford University and Samsung Advanced Institute of Technology describe the method in this week’s issue of Science.

Nanotube network: Atomic-force-microscopy images show semiconducting carbon nanotubes aligned on a spin-coated silicon wafer.

Carbon nanotubes have excellent electronic and mechanical properties that could enable smaller and faster transistors, which are essential elements in a range of electronic devices. Ultimately, researchers hope to make ultracompact computer chips in which transistors are made from single nanotubes. But thin films of carbon nanotubes, in which several nanotubes are used for each transistor, can also be useful. For example, carbon nanotubes transport electronic charges faster than the films of amorphous silicon used now in transistors that control pixels in displays. Carbon-nanotube-based displays, then, could be more responsive. They would also consume less power–an important consideration for portable electronics displays.

But carbon nanotubes have proved challenging to work with. Every batch of carbon nanotubes has both semiconducting and metallic varieties, but transistors need to switch on and off to control current flow, which only semiconducting nanotubes can do. As a result, techniques are needed to sort the different types of nanotubes. What’s more, the nanotubes must be carefully aligned to make working transistors. While other researchers have developed ways to either sort or align carbon nanotubes, the new method combines these two steps, which could make it attractive for manufacturing electronics. “We believe our approach is very practical, since the separation and alignment take place right at the surface, in a one-step process,” says Melburne LeMieux, a postdoctoral fellow at Stanford and the first author of the study.

To make carbon-nanotube transistors, the group refined what is called a random nanotube network, which involves depositing a carbon-nanotube solution onto a silicon wafer and spinning it rapidly to form a thin film of nanotubes. By chemically modifying the silicon wafer with either amine or phenyl groups, the researchers ensured that only one type of nanotube–semiconducting or metallic, respectively–would be absorbed onto the surface. The researchers showed that the process results in a film of carbon nanotubes with 90 percent of one or the other electronic type. They then added electrodes to the wafer to form transistors.

“It is hard to find an easier or simpler process than a one-step spin coating of a silicon wafer,” says Michael Strano, a chemical-engineering professor at MIT. “This is potentially a very low-cost method to creating thin-film transistors from single-walled nanotubes.” Although the films are not purely one electronic type or the other (a semiconducting film still has 10 percent metallic nanotubes), the researchers showed that the binding was selective enough to produce devices with useful electronic properties, such as high ratios between on and off states and the ability to quickly transport charge. The semiconducting surfaces showed an average on-off ratio of 100,000 to one, which the researchers say is the highest ratio achieved for carbon-nanotube films to date. Although on-off ratios for amorphous silicon are much higher (more than a million to one), the ability of the nanotube network to carry charges much more quickly compensates for this, by allowing the devices to perform faster. Nanotube-based transistors also require less voltage than silicon to be turned on, which reduces power consumption.

Because the spin-coating technique pulls the solution from the center toward the edge of the wafer, the absorbed nanotubes tend to align radially, so “devices will need to be designed to take this into consideration,” says Zhenan Bao, a professor of chemical engineering at Stanford. In conventional designs for transistors in displays, source and drain electrodes are aligned in a gridlike pattern over the entire wafer. They would still be placed opposite each other on the radially aligned nanotubes, but the orientation of each electrode pair on the wafer would vary. While the group is working to align the nanotubes along one direction on the wafer, “it would be best if we could control the process for more than one type of alignment,” LeMieux says.

Another important factor for any sorting technique is whether it can be scaled up for commercial manufacturing. “We have tested this process on five-inch wafers, and it works,” says Bao, whose first tests used a wafer only 12.7 millimeters in diameter. The five-inch wafer is big enough for many commercial devices, such as cell-phone or computer screens. In addition to making semiconducting films, the researchers are developing films of conductive nanotubes. The group is working with other surfaces that might have stronger interactions and could lead to higher nanotube absorption density, which is especially important for conducting surfaces. The team will also explore the fundamental absorption mechanisms responsible for nanotubes binding with each different surface.

“While there is still more work to be done, depositing aligned nanotubes on a wafer scale and effectively eliminating the background presence of metallic nanowires represent two very significant steps toward an economical, commercially viable nanotube electronics manufacturing technology,” says Peter Burke, leader of the Nanotechnology Group at the University of California, Irvine.

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