A Collection of Articles
Edit

Energy

Tomorrow's Transistor, Built Atom by Atom

A more precise manufacturing method will help as electronics shrink ever smaller.

Applied Materials, the world’s leading supplier of manufacturing equipment to chipmakers, has announced a new system for making one of the most critical layers of the transistors found in logic circuits.

Chip stack: This illustration shows the layers that make up a gate in a 22-nanometer transistor. The white balls on the bottom are silicon. The light blue balls in the middle are silicon dioxide molecules; the larger turquoise balls higher up are hafnium oxide; and the yellow balls are nitrogen atoms.

Applied Materials’ new tool, announced at the Semicon West conference in San Francisco on Tuesday, deposits a critical layer in transistors one atom at a time, providing unprecedented precision.

As chipmakers scale transistors down to ever-smaller sizes, enabling speedier and more power-efficient electronics, atomic-scale manufacturing precision is a growing concern. The first chips with transistors just 22 nanometers in size are going into production this year, and at that size, even the tiniest inconsistencies can mean that a chip intended to sell at a premium must instead be used for low-end gadgetry.

Transistors are made up of multiple layers: an active silicon material topped with an interfacing layer and then a layer of a material called a dielectric, which makes up the “gate” that switches the transistor on and off.

Applied Materials sells equipment for depositing these layers, called the gate stack, on top of silicon wafers. In the switch from today’s 32-nanometer to the next generation of 22-nanometer transistors, it’s become trickier to make the gate. The interface and dielectric layers both have to get thinner, and the behavior of the layers can be affected by tiny flaws where the materials touch. And as the layers get thinner, tiny flaws can be magnified even more than in larger transistors made from thicker layers.

Manufacturing accuracy will be even more important in the next-generation three-dimensional transistors that chipmaker Intel will begin producing later this year. In these devices, the active area is a raised strip that the interface and gate layers contact on three sides. This increased area of contact helps these devices perform better, but it also means an increased vulnerability to flaws.

The process uses atomic-layer deposition, or ALD, which lays down a single atomic layer of the dielectric at a time. This method is more expensive, but it’s become necessary, says Atif Noori, global product manager of Applied Materials’ ALD division. For the heart of the transistor—the gate—to work, “you have to make sure you’re putting all the atoms right where you want them.”

One source of inconsistencies in microchips is exposure to air. In Applied Materials’ new tool, the entire process of depositing the gate stack is done in a vacuum, one wafer at a time. Making the gate stack entirely under a vacuum also leads to a 5 to 10 percent increase in the speed at which electrons travel through the transistor; this can translate into power savings or faster processing. Ordinarily, there’s significant variation in the amount of power it takes to turn on a given transistor on a chip; manufacturing under a vacuum tightens that distribution by 20 to 40 percent.

Uh oh–you've read all five of your free articles for this month.

Insider basic

$29.95/yr US PRICE

Subscribe
What's Included
  • 1 year (6 issues) of MIT Technology Review magazine in print OR digital format
  • Access to the entire online story archive: 1997-present
  • Special discounts to select partners
  • Discounts to our events

You've read of free articles this month.