Speedier Nanotube Circuits
A new method produces dense arrays of carbon nanotubes for digital logic.
Researchers have developed a new way of producing very dense arrays of carbon nanotubes suitable for making complex integrated circuits.
Nanotube transistors have shown great promise in simple experimental prototypes, but making them into the complex circuits—needed for the chips that run computers and cell phones—has proven tricky. Researchers at Stanford University are using the new fabrication method to build ever more complex circuits that they hope will soon rival the speed of silicon.
For years, computer scientists have worried that, as they continue to miniaturize silicon transistors in order to cram more computing power in ever-smaller spaces, they will come up against the material’s physical limits. Many replacements are being explored, including exotic semiconductors and another form of carbon called graphene. For digital logic, though, many believe carbon nanotubes show the greatest promise. “No other material has shown the same ability to scale down as aggressively as carbon nanotubes can,” says Aaron Franklin, a researcher at IBM’s Watson Research Center in Yorktown Heights, New York. When silicon transistors are miniaturized to a comparable size scale, they become leaky and unstable.
However, making a single high-performance nanotube transistor is one thing; making a large array of nanotubes integrated into a circuit is quite another. In the past few years, researchers at Stanford have made some of the most complex nanotube circuits yet. They developed workarounds to overcome carbon nanotubes’ imperfections—the presence of metallic tubes amongst the semiconducting ones needed for transistors, for example. But these circuits were still relatively simple, performing arithmetic at about the level silicon circuits achieved in the 1960s.
The bottleneck has been making dense arrays of well-aligned carbon nanotubes. Stanford professors H-S Philip Wong and Subhasish Mitra previously used a stamping technique to transfer well-aligned nanotubes grown on quartz to a silicon-dioxide wafer for fabrication into transistor arrays and circuits. But there weren’t very many nanotubes in each transistor to carry the current, and the low-current transistors didn’t have high enough output to be made into complex circuits. That’s because the Stanford researchers were only able to do one transfer step before the nanotubes became tangled up into a mess that couldn’t be made into a transistor. When researchers try to lay down more nanotubes hoping for a proportional increase in current, says Mitra, “all sorts of weird interactions happen and sometimes you actually get less current.”
The same researchers have now developed a method for holding down layers of nanotubes while more layers are deposited on top. “The nanotubes are like fragile threads that want to interact with one another,” says Mitra. “We had to add a thin layer of a solid in between to protect them.”
The Stanford researchers put down a thin layer of gold with each stamp. Once the gold and nanotubes are in place, the researchers etch away areas of gold where they want to place each transistor’s electrical contacts. They then fill these holes with a metal contact material such titanium and palladium. Finally, they etch away the rest of the gold. This entire structure is built up on top of a silicon dioxide wafer patterned with back gates for the transistors. This work is described online this week in the journal Nano Letters.
Mitra says it should be possible to perform several transfers for for a density of 100 to 200 nanotubes per micrometer. The transfer technique is also compatible with techniques the group has developed in the past to deal with stray metallic nanotubes and the occasional misplaced nanotube.
“Nanotubes are messy to work with today,” says Franklin. But “there is no fundamental bottleneck that says this can’t be done.”
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June 11-12, 2019