Sometime in the coming decades, chipmakers will no longer be able to make silicon chips faster by packing smaller transistors onto a chip. That’s because silicon transistors will simply be too leaky and expensive to make any smaller.
People working on materials that could succeed silicon have to overcome many challenges. Now researchers at the University of California, Berkeley, have found a way past one such hurdle: they’ve developed a reliable way to make fast, low-power, nanoscopic transistors out of a compound semiconductor material. Their method is simpler, and promises to be less expensive, than existing ones.
Compound semiconductors have better electrical properties than silicon, which means that transistors made from them require less power to operate at faster speeds. These materials are already in some expensive niche applications such as military telecommunications equipment, which gives them a leg up over more exotic potential silicon replacements like graphene and carbon nanotubes.
But wafers of compound semiconductor materials are also very fragile and expensive, “which is only okay where cost doesn’t matter,” says Ali Javey, associate professor of electrical engineering and computer sciences at the University of California, Berkeley. Compound semiconductors are on the market in expensive communications chips for the military, for example.
Researchers believe they can overcome this fragility and expense by growing compound-semiconductor transistors on top of a supportive silicon wafer—a trick that should be compatible with existing manufacturing infrastructure.
However, compound semiconductors cannot be grown on silicon—there’s a mismatch between the crystalline structures of the two materials that makes this difficult to do well. The Berkeley group has now shown that transistors made from compound semiconductors can be grown on another surface and then transferred to a silicon wafer. “That’s a plausible path for dealing with the fact that compound semiconductors are difficult to grow,” says Jesús del Alamo, professor of electrical engineering and computer science at MIT who was not involved with Javey’s work.
The Berkeley researchers demonstrated their technique using indium arsenide. They grow the material on top of a wafer of gallium antimonide protected by a sacrificial top layer of aluminum gallium antimonide. The wafer enables the growth of a high-quality, crystalline indium-arsenide film, and the sacrificial layer can then be chemically etched away, releasing nanoscale indium-arsenide strips. The researchers pick up the nanoribbons with a rubber stamp and place them on top of the silicon wafer. The silicon provides structural support for the indium arsenide. It’s coated with silicon dioxide, which will act as the insulator in the transistors. The transistors are completed by laying down metal gates to bring electricity in and out.
Javey’s group describes the performance of indium-arsenide transistors made in this way in a paper published online last week in the journal Nature. The transistors, which are 500 nanometers long, perform as well as compound-semiconductor transistors made using more complex techniques, Javey says. And the Berkeley group’s indium-arsenide transistors are much faster than their silicon equivalents, while requiring less power—half a volt as compared with 3.3 volts. Their transconductance—how responsive they are to changes in voltage—is eight times better than that for a silicon transistor this size. “Given how these devices were prepared, this performance is quite impressive,” says MIT electrical engineering professor Dmitri Antoniadis.
Javey notes that the process required to make the indium-arsenide transistors is similar to that used to make a class of chips called silicon-on-insulator (SOI) electronics, which require a slice of silicon to be placed on a wafer of another material during manufacturing. For that reason he’s named them XOI—anything on insulator.
The process for making the XOI devices at wafer-scale would be more complex than SOI because it might require integrating several different types of materials built on wafers of different sizes, says Michael Mayberry, director of components research at Intel. “There are lots of ways that process could go wrong,” he says. For the past three years, Intel has been working on processes for growing compound semiconductors on silicon wafers directly, by growing a buffer layer in between them. So far, they have to use a very thick buffer that impedes the performance of the transistors, but Mayberry says they have proven that the concept can work.
The value of Javey’s work, Mayberry says, is that it demonstrates that the indium-arsenide transistors perform well when shrunk down to the nanoscale. “We don’t know how these devices will behave,” he says. Theorists have made guesses, he says, but at the nanoscale, unexpected quantum effects can crop up.
Javey plans to make the transistors much smaller and see whether they maintain their performance. MIT’s del Alamo and Antoniadis are trying to determine the ultimate scaling of compound-semiconductor transistors; the pair have made transistors that are 30 nanometers long. “I would like to see what perfection of materials can be achieved at a small scale,” says Antoniadis.