Samsung's Plan for Terabit Flash Memory
New fabrication technology improves memory capacity without increasing chip size.
Researchers at Samsung, one of the leading producers of flash-memory chips, recently announced a new chip that can hold twice as much data as before, and without an increase in its footprint on a circuit board. They were able to double the data capacity by building chips with multiple layers of silicon, creating 3-D structures. At the International Electron Device meeting in San Francisco last week, lead researcher Soon-Moon Jung said that by combining today’s chip-making processes with the new 3-D design, they could build a one-terabit flash chip composed of eight layers of silicon.
Flash memory is found in all sorts of gadgets, from mobile phones and USB drives to MP3 players and laptops (see “Flash for Laptops”). In recent years, it gained popularity because, unlike the spinning disks of magnetic hard drives, flash is a solid-state memory (made of silicon), making it less prone to damage. And, unlike other types of solid-state memory, such as random-access memory, flash is nonvolatile, meaning it can retain data without power.
Because flash-memory chips are made with silicon, their storage capacity has consistently increased, while chip size has shrunk. But, like microprocessors, flash memory will face fabrication hurdles in the next few years. Right now, the features on many flash-memory chips are about 60 nanometers wide. Some engineers estimate that today’s lithography systems, used to pattern and carve out these features, will only be able to keep shrinking them until about 2009. And even then, the chips face physical limitations. Samsung’s Jung says that with features smaller than 30 nanometers, electrical charges stored in a flash-memory cell will start to leak, meaning data will be lost.
So the Samsung researchers set out to find a way to use existing fabrication technology to increase flash capacity. Jung says that two elements were key: minimizing the amount of extra area used for their stacking architecture, and keeping the number of extra fabrication steps to a minimum, so as not to drive up costs.
The researchers turned to a process previously used at Samsung to make 3-D stacks of static random-access memory. The process uses a high-quality, single-crystal silicon substrate to build the first layer of memory cells. That layer is then used as a foundation on which to build a second layer, also composed of single-crystal silicon.
Essentially, a single layer of flash is analogous to a parking lot: electrons fill up memory cells much as cars fill up parking spots. Adding another layer of silicon increases the data capacity just as a two-story parking garage can hold more cars than a one-story parking garage can.
The trouble with this 3-D layering method is that it tends to take up space on the first layer, which could be used as memory cells, says Vivek Subramanian, professor of electrical engineering at the University of California, Berkeley. The only way to grow a layer of crystalline silicon is by using another silicon layer as a seed, he says. Growing this second layer requires opening up “windows” in the first layer, potentially taking away space that could be used to store data.
Samsung’s challenge, then, was to minimize the area that these windows take up by strategically distributing them, in much the same way that columns are used as structural supports in parking garages.
Another trick the researchers used, says Jung, was to simultaneously fabricate the wire interconnects used for communication between layers and beyond the chip. If the wires were added separately, the 3-D chips would be much more expensive to make, due to the extra steps involved in ensuring communication between layers.
Making the layers comparable in terms of performance was another challenge. Due to the electrical nature of the second layer (it’s not grounded), only one memory cell can be erased at a time. In contrast, memory cells in the first layer can be erased in large chunks. In the researchers’ prototype the second layer of memory cells initially took 32 times longer than the first to erase the same amount of data. Jung says the researchers overcame this challenge by designing a novel electrical scheme that grounds the second layer so that data can be erased in chunks and at the same speed as the first layer.
The prototype memory chip announced in San Francisco is still in its early stages and only has a capacity of 32 bits. Still, the results are encouraging. “I think it’s an interesting demonstration of concept,” says Subramanian. “The fact that they got it to work and they’re getting very good electrical data, and the fact that the multiple layers built on top of each other work pretty nicely, is attractive.”
Yet Subramanian cautions that the technology for 3-D flash still needs to prove its manufacturability. Even with Samsung’s results, adding layers of silicon increases the number of steps in the process and ultimately makes the chip more expensive. “Flash memory is very driven by price, and it’s a very cutthroat business,” he says.
Bruce White, manager of advanced CMOS at Freescale Semiconductor, sees great promise in 3-D fabrication technologies for flash memory and beyond. “We see it as very important,” he says. Not only could the capacity of solid-state storage increase significantly without taking up more chip real estate, but engineers could also mix and match solid-state devices to fit different applications. For instance, one layer could be flash, and another layer could be dynamic random-access memory, both fitting together like Lego blocks, White says. “We would like to be able to combine different technologies all on the same substrate.”
Although Samsung didn’t offer a specific timeline for its 3-D flash memory, Jung says that it could “be rapidly deployed because it can fully utilize existing 2-D planar technology.”
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