The first three-dimensional carbon nanotube circuits, made by researchers at Stanford University, could be an important step in making nanotube computers that could be faster and use less power than today’s silicon chips. Such a computer is still at least 10 years off, but the Stanford work shows it is possible to make stacked circuits using carbon nanotubes. Stacked circuits cram more processing power in a given area, and also do a better job dissipating waste heat.
A recent IBM study showed that for a given total power consumption, a circuit made from carbon nanotubes is five times faster than a silicon circuit. “We can make silicon transistors smaller and smaller, but at extremely small dimensions they don’t show the desired performance anymore,” says Zhihong Chen, manager of carbon technology at the IBM Watson Research Center. “We are looking to alternative materials that can be scaled more aggressively but still maintain device performance.”
Researchers have had great success in making single nanotube transistors in the lab, but scaling them up to make complex circuits has been difficult because it’s impossible to control the quality of every single nanotube. The Stanford circuit designs, which were presented last week at the International Electron Devices Meeting in Baltimore, make it possible to create more complex nanotube circuits in spite of the material’s limitations.
“When we deal with a large number of nanoscale components, we can’t demand everything to be perfect,” says H.-S. Philip Wong, professor of electrical engineering at Stanford. When the Stanford researchers grow arrays of nanotubes to make circuits, they get a mix of semiconducting nanotubes and metallic nanotubes that will cause electrical shorts if they’re not eliminated. Some of the nanotubes grow in straight lines, but some are squiggly, and these must also be worked around. While chemists work on methods for growing straight, pure nanotubes, the Stanford researchers’ question, Wong says, is, “How do we mitigate that and make sure the system still works?”
The answer is to account for materials limitations in the circuit designs. “We have to find a way to build with the metallic nanotubes so that they don’t make trouble,” says Subhasish Mitra, professor of electrical engineering and computer science at Stanford. The Stanford group first makes what Mitra calls a “dumb” layout. Using a stamp, researchers transfer a flat-lying, aligned array of carbon nanotubes grown on a quartz substrate to a silicon wafer. They then top the nanotubes with metal electrodes. At the surface of the wafer, between the silicon and the nanotubes, is an insulating layer that acts as a back gate, allowing the researchers to switch the semiconducting nanotubes off before using the metal electrodes to burn out the metallic nanotubes with a blast of electricity. A top gate is added that’s patterned in such a way that it won’t connect with any misaligned tubes. The circuits are then etched to remove metal electrodes that aren’t needed for the final circuit design.
To make a three-dimensional circuit, the researchers simply repeat the stamping and electrode-growth procedures to stack as many layers as are needed before the final etching process. The nanotube stamping process, which the Stanford group first demonstrated last year, is key to creating stacked layers because it can be done at low temperatures that don’t melt the metal electrical contacts in underlying layers.
While materials scientists are still working on how to grow batches of carbon nanotubes where every single one is semiconducting, the Stanford group is working around the problem. “Instead of burning out one tube at a time, they do it at the circuit level, then design the circuits smartly to get around the burned-out tubes,” says IBM’s Chen.
“They’ve demonstrated small, simple circuits, like what was done in the mid-1960s with silicon,” says Shekhar Borkar, an Intel fellow and director of the company’s microprocessor technology lab. The Stanford group has made, for example, a simple calculator that can add and store numbers.
The Stanford group is currently working to make ever more complex integrated circuits. “So far as complexity is concerned, there is fundamentally no barrier” on carbon nanotubes, says Mitra. Materials barriers remain, however. The Stanford nanotube arrays are some of the densest ever made, with five to 10 nanotubes per micrometer, but this isn’t enough. “We need 100 nanotubes per micrometer to get really good performance,” says Wong.