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Highest Capacity Flash Memory Yet

Double the normal number of bits are crammed into each memory cell.
February 12, 2009

Even with the electronics industry in the economic doldrums, memory-card maker SanDisk is betting that customers will be willing to pay to put more data in their pocket.

Memory multiplied: A micrograph of a 64-gigabit flash chip, which can store four bits per memory cell–double the amount traditionally stored.

The company has announced a significant advance in flash-memory technology that enables 64 gigabits of data to be stored on a chip the size of a fingernail. The new, more spacious flash chips do this by holding four bits per memory cell, as opposed to the standard one or two bits per cell. SanDisk presented details of the advance at the International Solid State Circuits Conference in San Francisco on Tuesday.

“Developing a four-bit-per-cell chip is a massive challenge, and we consider this to be a major breakthrough,” says Khandker Quader, senior vice president of memory technology and product development at SanDisk. Quader adds that the work presented at the conference, which focuses on ensuring that data is stored reliably, has implications for generations of flash memory to come.

Flash memory has become a mainstay of the electronics industry. It is used in many gadgets, including cameras, game consoles, cell phones, and the latest laptops. Because data is stored on a flash chip as electrical charge on transistors, flash memory is subject to the famous credo set forth by Gordon Moore of Intel decades ago: that the number of transistors on a chip will double every two years. In other words, thanks to the shrinking size of transistors, flash memory just keeps getting more capacious.

In recent years, however, engineers have found another way to increase the capacity of flash drives, without waiting for the transistors to shrink. They do this by storing more than one bit of data per transistor, within what are referred to as multilevel cells (MLCs). In a single-level cell, data is stored using two distinct states, defined by different voltage levels. In contrast, a four-bit MLC stores information in 16 states, which translates into four bits of data per cell, or four times the amount of information.

This trick is by no means easy. Ensuring that each memory cell maintains precisely the right voltage, without disturbing that of neighboring cells, is a major challenge, says Quader. Another issue is reducing the time that it takes to write to these cells.

SanDisk tackled these problems with new algorithms that run on a flash-memory chip controller. In order to write and read data to and from cells, engineers employ some of the transistors on a flash chip to control the other transistors used to store data. These algorithms are significant factors in reliably cramming in four bits per cell.

“We’ve introduced a number of key concepts that allow us to manage the memory side of it,” says Quader. “The complexity of this distribution is so much different than what you’re doing with two bits per cell.”

Usually, a single applied voltage is used to write data to a memory cell, but this approach won’t work with four-bit cells because they are so small and close together. Writing to one cell can easily erase a neighboring cell due to electrical coupling effects. Using an approach called three-step programming gets around this problem. A small voltage is applied to one cell, effectively programming only 3 of its 16 states. Next, the neighboring cells are programmed to 15 and 3 levels respectively, using different voltages. Finally, the original cell is programmed a second time. Writing data in this stepwise manner produces electrical characteristics within the cell that ensure reliable storage of bits.

Because the programming scheme takes slightly longer than do traditional approaches, SanDisk developed a feature that senses the voltages stored within cells by effectively remembering the values sensed previously. The end result is a chip that can write data at a rate of 7.8 megabytes per second–close to the speed at which existing chips can be accessed. SanDisk’s Quader says that the 64-gigabit chips will be in production before the second half of this year, using 43-nanometer lithography technology.

Mark Bauer, a research fellow at memory company Numonyx and chair of the conference session, says that the real innovation behind SanDisk’s work is the controller technology. “You won’t see four-bit flash without that controller,” he says.

Bauer adds that, while some experts have predicted that flash memory is reaching its storage limits, clever engineering keeps breathing new life into the technology. “Four years ago, people were saying that flash was hitting a roadblock, but the improvements keep coming,” he says. “We can’t tell what solutions being explored today will solve the problems tomorrow.”

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