These are challenging times for computer chip engineers. A technology the industry has been counting on to etch the tiny features of the next few generations of chips is still not ready.
Known as extreme ultraviolet lithography, or EUV, the technology is years behind schedule. Although the approach works, UV light sources powerful enough to etch chips quickly enough for mass production are lacking. In 2012, Intel invested $4 billion in the Dutch company ASML, a supplier of manufacturing equipment, to bolster work on perfecting the technique (see “The Moore’s Law Moon Shot”). Leading chip makers Samsung and TSMC have since each added $375 million of their own to ASML’s research effort, but there is still no indication as to when EUV might be ready.
A radical alternative to conventional lithography now looks increasingly viable. Known as directed self-assembly, it involves using solutions of compounds known as block copolymers that assemble themselves into regular structures. Block copolymers are made up of different units (the blocks) that prefer to be separate, like oil and water; left alone, these compounds typically produce swirling, fingerprint-like patterns. But if guided by a “pre-pattern” of chemical guides made with conventional lithography, the block copolymers produce lines and other regular patterns. Crucially, those final patterns can have much smaller details than those of the pre-pattern. A final pattern made in this way can then be used as a template for the chemical processes that etch features into a silicon wafer—the same process that is the end point of conventional lithography.
An Steegen, senior vice president for process technology development at IMEC, a micro-electronics research center in Leuven, Belgium, said at the Semicon West semiconductor industry conference in San Francisco on Wednesday that self-assembly looks capable of extending the working life of existing lithography, as an alternative to switching to EUV. IMEC can now pattern transistor-like structures with a design that’s similar to those of Intel’s latest chips and features as small as 14 nanometers, she said. “We’re all desperately waiting for EUV to be ready, but there are alternatives,” she said.
IMEC installed the world’s first manufacturing line able to use self-assembly in its pilot fab in 2012. Work there has focused on reducing errors in self-assembled structures through improved materials and better pre-pattern designs. Steegen estimates that the technology could be ready for mass production sometime around 2017. That generation of transistors should have features as small as seven nanometers. The smallest transistors in commercial production today have features as small as 14 nanometers.
State University of New York also operates a pilot production line capable of directed self-assembly at its Center for Nanoscale Engineering in Albany. Christopher Borst, associate professor of nanoengineering, reported at Semicon that it could now reliably create arrays of repeating lines and fin-like structures as small as 18 nanometers. “We’ve developed some very impressive structures that could make their way into device processes,” said Borst. “The basic capability is shown for materials and manufacturability.”
However, self-assembly still isn’t fully compatible with mass production. Unsolved problems include finding ways to guarantee the purity of self-assembly materials to minimize defects, says Steegen. The industry will also have to develop tools to help chip designers work out the guiding patterns needed to cause a self-assembly mixture to create the desired final design.
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