Moving up: In a conventional transistor (left) a top-mounted gate controls the flow of electrical current through a flat silicon channel below. In Intel’s new design (right) the silicon channel is raised like a fin, so that the gate contacts it from three sides. This provides greater control over the flow of current through the channel, and reduces power leakage.
These three-dimensional transistors were first imagined and built by three researchers at the University of California, Berkeley, in the late 1990s, in response to a call from the United States Defense Advanced Research Projects Agency for designs that would allow transistors to scale below 25 nanometers, an order of magnitude smaller than the ones in production at the time. Chenming Hu wrote out the technical specs for the new transistor on a plane ride to Japan in 1996. A Berkeley group made up of Hu, Jeffrey Bokor, and Tsu-Jae King Liu first made these transistors, which they called FinFETs, in 1999.
“It was an instant hit,” says Hu. The university opted to release the intellectual property into the public domain instead of patenting it; as the Berkeley researchers kept refining the designs, Hu presented the work at several companies, including Intel. By 2002, the FinFET and a second Berkeley design, known as “silicon on insulator,” were the devices favored by the International Technology Roadmap of Semiconductors as the technologies likely to meet the industry’s needs in the next 15 years. But at Intel, at least, FinFET pulled ahead of the second design, which relies on adding a very thin layer of silicon to a transistor. Until about two years ago, the companies who make silicon wafers weren’t able to make the active layer thin enough. French company Soitec can now manufacture the necessary wafers for this alternate design, and Hu says Intel’s competitors may at some point adopt it.
Getting the promising three-dimensional device design out of the lab and into production took about a decade. Intel hasn’t disclosed many of the details of what fab upgrades are necessary to make the new transistors, but based on the fact that no new materials or machines are apparently required—and the marginal increase in production cost of 2 to 3 percent promised by the company—the changes appear to be minor. The company has said that making the three-dimensional channels only involves an extra etching step.
Hu says the Berkeley researchers decided from the start that their new design would have to be compatible with the industry’s existing infrastructure, and that has proved to be the case. The main hurdle in getting the technology ready for volume production, says Hu, was likely dealing with reliability: getting the dimensions of the very thin channel under control when billions of them must be made on every single wafer.
Hu says the Berkeley group designed these transistors so that they would not require circuit designers to completely redesign chip architectures. That’s part of the reason why Intel can get products out so quickly. Hu’s group has been working on circuit-simulation tools for the tri-gate transistors for the past five years.
Still, circuit designers see new opportunities that could open up with these transistors. They offer new ways of tuning the behavior of individual gates, which “gives designers new knobs to play with in order to further improve power efficiency and reliability,” says Subhasish Mitra, professor of electrical engineering and computer science at Stanford University. Seeing a totally new transistor go into volume production within the span of about a decade is an encouraging sign that the industry “is not stale” and that good technology ideas can still make it out of academic labs, Mitra adds.
Smaller design teams can now prototype and deploy faster.