Building up: The 32-nanometer transistor at left is used in Intel’s chips today; the company’s new three-dimensional 22-nanometer transistor is at right. In the new transistor, gates intersect with silicon “fins” that stand up from the chip’s surface and interact with the gate on three sides, a design that results in less leakage of current.
The company has been developing the tri-gate transistor since 2002. “The real challenge has been getting it ready for manufacturing,” says Mark Bohr, an Intel senior fellow. Bohr speculates that the company has a three-year lead over other chipmakers with this technology.
Intel says the production of the three-dimensional transistors won’t require any new manufacturing technologies. Extra etching steps will lead to a small production cost increase.
The company says the three-dimensional design will scale even further to the next generation of chips, which will use 14-nanometer transistors. Beyond that, it will need something new. “We’re really in an era where we can no longer shrink transistor sizes and expect significant benefits,” says Bohr. “We have to continually innovate and invent new structures and materials.”