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To make a three-dimensional circuit, the researchers simply repeat the stamping and electrode-growth procedures to stack as many layers as are needed before the final etching process. The nanotube stamping process, which the Stanford group first demonstrated last year, is key to creating stacked layers because it can be done at low temperatures that don’t melt the metal electrical contacts in underlying layers.

While materials scientists are still working on how to grow batches of carbon nanotubes where every single one is semiconducting, the Stanford group is working around the problem. “Instead of burning out one tube at a time, they do it at the circuit level, then design the circuits smartly to get around the burned-out tubes,” says IBM’s Chen.

“They’ve demonstrated small, simple circuits, like what was done in the mid-1960s with silicon,” says Shekhar Borkar, an Intel fellow and director of the company’s microprocessor technology lab. The Stanford group has made, for example, a simple calculator that can add and store numbers.

The Stanford group is currently working to make ever more complex integrated circuits. “So far as complexity is concerned, there is fundamentally no barrier” on carbon nanotubes, says Mitra. Materials barriers remain, however. The Stanford nanotube arrays are some of the densest ever made, with five to 10 nanotubes per micrometer, but this isn’t enough. “We need 100 nanotubes per micrometer to get really good performance,” says Wong.

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Credit: Stanford

Tagged: Computing, Materials, nanotechnology, silicon, electronics, carbon nanotubes, energy efficiency, nanotubes

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