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Because the spin-coating technique pulls the solution from the center toward the edge of the wafer, the absorbed nanotubes tend to align radially, so “devices will need to be designed to take this into consideration,” says Zhenan Bao, a professor of chemical engineering at Stanford. In conventional designs for transistors in displays, source and drain electrodes are aligned in a gridlike pattern over the entire wafer. They would still be placed opposite each other on the radially aligned nanotubes, but the orientation of each electrode pair on the wafer would vary. While the group is working to align the nanotubes along one direction on the wafer, “it would be best if we could control the process for more than one type of alignment,” LeMieux says.

Another important factor for any sorting technique is whether it can be scaled up for commercial manufacturing. “We have tested this process on five-inch wafers, and it works,” says Bao, whose first tests used a wafer only 12.7 millimeters in diameter. The five-inch wafer is big enough for many commercial devices, such as cell-phone or computer screens. In addition to making semiconducting films, the researchers are developing films of conductive nanotubes. The group is working with other surfaces that might have stronger interactions and could lead to higher nanotube absorption density, which is especially important for conducting surfaces. The team will also explore the fundamental absorption mechanisms responsible for nanotubes binding with each different surface.

“While there is still more work to be done, depositing aligned nanotubes on a wafer scale and effectively eliminating the background presence of metallic nanowires represent two very significant steps toward an economical, commercially viable nanotube electronics manufacturing technology,” says Peter Burke, leader of the Nanotechnology Group at the University of California, Irvine.

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Credit: Melburne LeMieux / Stanford University

Tagged: Computing, Materials, displays, carbon nanotubes, transistors

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