When Dai made transistors out of these ribbons, he measured on/off ratios of more than 100,000 to 1, which is attractive for transistors in processors. Previously, room-temperature on/off ratios of graphene ribbons had been measured at about 30 to 1.
Still, many obstacles remain to making graphene processors using Dai’s methods, says Walter de Heer, a physics professor at Georgia Tech. The ribbons made with Dai’s process have to be sorted. Pieces that are too large or not in the shape of ribbons have to be weeded out. There also needs to be a way of arranging the ribbons into complex circuits.
However, researchers already have ideas about how to address these challenges. For example, graphene ribbons have more exposed bonds at their edges, so chemicals could be attached to these bonds that would direct the ribbons to bind to specific places to form complex circuits, de Heer says.
The best way to make graphene electronics, however, may be to take advantage of the fact that graphene can be grown in large sheets, says Peter Eklund, a professor of physics at Penn State. If better lithography methods are developed to pattern these sheets into narrow ribbons and circuits, this could provide a reliable way of making complex graphene-based electronics.
Ultimately, the most important aspect of Dai’s work could be the fact that it has demonstrated electronic properties that were only theoretical before, Eklund says. And this could lead to even more interest in developing graphene for next-generation computers. “Once you get a whiff of narrow graphene ribbons with a high on/off ratio, this will tempt a lot of people to try to get in there and either make ribbons by high-technology lithographic processes, or try to improve the approach developed by Dai,” says Eklund.
Smaller design teams can now prototype and deploy faster.