Using fewer read-write heads per bit is a more compact arrangement than conventional solid-state memory. This is particularly the case if the nanowires are oriented perpendicularly to the surface of the chip, such that they grow vertically from the surface, or are deposited in wells carved into the chip. In this case, 100 bits might be stored in the same area as one bit in a conventional device. This arrangement is key to making memory denser and also less expensive.
Critical to the technology is finding a way to shuttle bits along the length of a nanowire. In Parkin’s memory, bits of information would be stored by creating or removing magnetic boundaries called domain walls within magnetic nanowires. These domain-wall bits create distinctive magnetic fields that can be read with conventional devices. Researchers have long known that these walls can be moved using magnetic fields, but the walls would move in the same direction, annihilating each other. The key to making the device work was the discovery that electronic currents in magnetic materials can move these walls along a nanowire, and move them all in the same direction. That makes it possible to shift bits around to be read by single reading and writing devices.
Before such memory devices will be on store shelves, there are a couple of problems that need to be solved. First, the current required to move the domain walls is far too high to be practical. Parkin says that he’s making progress on this front, having discovered that the current can be reduced by adjusting the frequency of short bursts. He’s also working with new materials that may require less current.
A second challenge is getting a better understanding of the behavior of domain walls. For example, it’s not clear how defects in a nanowire can affect their behavior, or how closely the domain walls can be spaced. The answers to these questions may determine just how much more dense the memory will be, says Stuart Wolf, a professor of materials science and engineering at the University of Virginia. Wolf also notes that it will be difficult to reach the speeds of DRAM, since there will be some delay involved in shuttling domain walls along a nanowire.
The researchers will probably start with a simple version of the technology, in which the nanowires are arranged horizontally on a chip, rather than vertically. This will still allow the memory chips to be about as dense as flash memory, but with far faster performance and greater reliability than flash. If that’s successful, it would justify spending more money on even more compact devices using vertical nanowires, Parkin says.