Today, MIT spinoff Tilera announced that it’s shipping a computer chip with 64 separate processors whose design differs drastically from that of the chips found in today’s computers. The new chip, called Tile64, avoids some of the speed bottlenecks inherent in today’s chip architecture, and it can operate at much lower power, says Anant Agarwal, founder and chief technology officer of Tilera, based in Santa Clara, CA. Initially, Tile64 will be used in video applications such as videoconferencing systems, and in network hardware that monitors traffic to reduce e-mail spam and viruses.
Chips with multiple processing units, or “cores,” are nothing new. But by allowing the cores to communicate directly with each other, Tilera has addressed a widespread concern about the viability of adding more cores to microprocessors. “Every processor in the market today is a multicore,” says Agarwal. “The hope of the industry is to double the number of cores every 18 months. My prediction is, by 2014, we will have 1,000-core architectures. But the problem is, [current] architectures don’t scale.”
In existing multicore chips, each core communicates with the others via a set of wires called a bus. Performance doesn’t necessarily suffer when two or four cores share a bus, but when 16 or more cores try to use it simultaneously, data can get backed up. Agarwal explains that Tilera’s chip has no central bus. Instead, each core is connected to all the others. Also on each core is a full-featured processor, which can run an operating system, and memory caches, which hold data that needs to be quickly accessed.
In effect, the Tile64 has a mesh structure that’s similar to that of the Internet, a network in which there are many decentralized nodes. One reason the Internet is able to pass around data so quickly is that packets of information are sent through a vast network and can avoid traffic jams. If everyone’s e-mail had to go through a central server, there would undoubtedly be delays. Tilera’s microprocessor, says Agarwal, “is very much like the Internet on a chip.” And like the Internet, Tilera’s chip can be scaled up gracefully; it doesn’t need to be redesigned each time new cores are added.
The idea of using mesh architecture for multicore chips has been explored for at least a decade, in research labs at MIT, Stanford, and the University of Texas, Austin. And recently, Intel announced a prototype 80-core chip based on a mesh. But Tilera is the first company to offer a product that uses the new architecture.
“Having a lot of cores is good, but they must be able to communicate with each other at high data rates,” says Jerry Bautista, codirector of Intel’s terascale-computing research program. “There are advantages to using a mesh … You can deal with traffic jams pretty easily.” Bautista says that Intel researchers are trying to find the best way to implement mesh architectures–among other experimental designs–in future chips. But he also cautions that making massively multicore systems work efficiently isn’t as simple as redesigning the hardware.
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