Many experts believe that carbon nanotubes could eventually replace silicon in microelectronics because of their potential for superior speed and reduced power consumption. And over the past several years, researchers have made transistors out of carbon nanotubes. However, it’s still difficult to make reliable circuits out of them. One problem is that the nanotubes, used for transistors that make up the circuits, tend to be fabricated in different directions, making it impossible to know which nanotube form which transistor. And such a chaotic arrangement can lead to electrical malfunctions. But now researchers at Stanford University have written a program that finds a working circuit layout, no matter how disorganized or misaligned the nanotubes.
“Just having a single [carbon nanotube] transistor isn’t going to do it,” says Subhasish Mitra, assistant professor of electrical engineering and computer science at Stanford. It may not be possible to synthesize precisely organized nanotubes anytime soon, so Mitra and his team, which includes Stanford electrical-engineering professor H.-S. Philip Wong, University of Southern California chemistry professor Chongwu Zhou, graduate student Nishant Patil, and Jie Deng of Stanford electrical engineering, have turned to algorithms to make sense out of the nanotubes mess.
Circuits are made of logic gates that collectively generate instructions to, say, send a document to a printer or turn on a cell phone. Transistors are at the core of these logic gates, grouped in various ways to make up different types of gates. The researchers first approached the problem of making nanotube circuits by looking at a specific type of digital logic gate called a 2-input NAND gate, which contains two parallel transistors that can messed up by misaligned nanotubes. If electrical current flows through one or both of the transistors, then the gate is “on.” If electrical current flows through neither, then the gate is “off.” But if the transistors are haphazardly arranged, these gates can’t operate properly.
“Even if current flows through neither of the transistors, the gate may be turned on by misaligned nanotubes,” says Mitra, “and if you try to complete a logic function, it could create a short or give a wrong response.” What his algorithm does, he explains, is find a way to lay out a circuit that keeps these nanotubes from creating shorts or incorrect logic gates.
To do this, the algorithm uses a combination of the mathematics of complicated networks and Boolean algebra to define various regions on a batch of nanotubes. Depending on the desired function of the circuit, a design is proposed that lays out legal and illegal regions for the gates to exist. When nanotubes cross the boundary into a particular region, explains Mitra, they are chemically etched away so that they won’t conduct an erroneous current to another transistor. The researchers have generalized the approach so that it works not just for NAND gates, but for any arbitrary logic gate as well.