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“Putting a tensile film over one type of transistor and a compressive film over another is pretty tricky,” says Nick Kepler, AMD’s vice president of logic technology development. “We found a way to do strained silicon on negative and positive transistors simultaneously and we used conventional materials.”

Instead of using the exotic silicon germanium, which others like Intel have done, AMD and IBM have managed to get by with the more familiar silicon nitride. By sticking with a conventional process, says Kepler, yield should be higher and costs lower.

“Silicon germanium is more costly and adds more complexity to the manufacturing flow,” he says. “There are many issues associated with it when you add materials or etch the cavity, and creating the strain is more complex.”

The DSL approach applies a compressive film over the entire chip and then etches the material away from the negative transistors. A tensile strain film is then applied universally and etched away from the P-type transistors.

For any given chip, strained-silicon chip makers can select an optimum tradeoff between power consumption and speed. With DSL, tuning for performance/power tradeoffs can be done at two stages.

 “During fabrication, we can make very slight changes, making the transition gates longer or thicker to reduce leakage,” Kepler says. “Or later we can turn down the voltage on the part.”

Either way, AMD and IBM promise to further improve power efficiency and reduce heat by integrating DSL with the duo’s previously introduced Silicon-On-Insulator technology, which adds a thin insulating layer between substrate layers to minimize leakage.

DSL technology is already being incorporated into older 130nm designs, and it will be added to AMD’s new 90nm dual-processor Opteron chips this fall. According to Kepler, DSL has been successfully tested with next-generation 65nm designs, and he expects it to work fine when they shrink their processors to 45nm, as well.

The AMD/IBM advantage may not last long. By the end of year, Intel should introduce its first 65nm processors, which include an improved form of germanium-based strained silicon that Intel claims will provide 30-percent speed increases over non-strained chips.

The basics of strained silicon technology have been known for over a decade, but warping silicon hasn’t been a priority because it was far easier to meet Moore’s Law by scaling down transistors. Beyond 45nm, however, it will become considerably trickier to gain the same performance improvements with consistent yield without undue power consumption and heat.

Yield is also an issue with strained silicon, as defects tend to crop up when you warp silicon. This may be particularly true with germanium. Texas Instruments, for example, is working on a strained silicon technology that uses the absolute minimum of germanium in order to reduce defects.

A year from now we should know whether Intel has solved the germanium yield problem or whether AMD and IBM were smart to stick with silicon nitride. For consumers, though, the important point is that semiconductor manufacturers are finally placing power efficiency at an equal priority as speed. After all, speed doesn’t matter if your battery runs out.

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