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Moore’s Law, which states that transistor density doubles every 18 months, has bumped against the laws of physics. And chipmakers are feeling the bumps.

As they push into “deep submicron” territory at .13 micrometers and below, the light waves produced by the lithographic equipment that etches designs onto silicon wafers are wider than the transistors.

And there’s another huge bottleneck in packing in transistors ever more tightly-the interconnects (aluminum or copper wiring) that link the transistors.

An industry group proposes a better solution for interconnects: X Architecture, which lets interconnects be drawn at 45-degree angles, rather than confined to the rectangular “Manhattan” grid that has been the norm since the mid-1980s.

What’s Known about X

Because diagonal interconnects can carry electrical signals over shorter distances, X Architecture chips will run 10 percent faster and consume 20 percent less power, says Steve Teig, chief technology officer at Simplex Solutions of Sunnyvale, CA, a vendor of testing software and design services. “It’s so silly that existing chips have these artificial restrictions,” Teig says.

Manufacturers can squeeze 30 percent more transistors onto each wafer, reducing per-chip costs. Diagonal routing also improves chips’ signal-to-noise ratios, raising yields and helping to further reduce costs, Teig says.

X Architecture isn’t appropriate for every type of chip. It works for logic-intensive chips with five or more layers, such as central processing units and digital signal processors, and isn’t needed for simpler products such as memory chips.

Simplex had no easy task when it began developing the key breakthrough, called liquid routing, with Toshiba two years ago. “We had to touch 50 different steps and invent a bunch of new technologies,” Teig says. The resulting gridless wiring scheme lets designers place diagonal interconnects at any one of eight angles.

Taking the Initiative

Diagonal routing itself isn’t new; for years it’s been employed in localized areas of some chips. What is new is the arsenal of design and manufacturing tools from a consortium of “X Initiative” vendors.

The 11 charter members represent key steps in production, from Numerical Technologies of San Jose, CA, a subwavelength design-tool vendor, to Etec Systems of Hayward, CA, which builds equipment for making the photomasks for transferring circuit patterns onto silicon.

Toshiba, which co-developed the enabling technology and the first design of a RISC processor core with Simplex, says it will begin making X-architecture chips in 2002. Last June, Panasonic brand maker Matsushita Electric Industrial became the second chipmaker to join.

You Say You Want an Evolution

The X Initiative’s work will be eased by a built-in advantage of the architecture: it allows diagonal routing only in a chip’s fourth and fifth metal layers. This makes it compatible with existing designs for memory cells and other chip components residing on the first three layers, and therefore with associated design tools. End-stage manufacturing processes can accommodate X Architecture without change, according to Teig, though companies all along the supply chain have the opportunity to sell optimized tools and services for it.

Numerical Technologies, for example, supports X Architecture with its existing tools. “We’re just beginning our work on the X Initiative,” says Michael Sanie, the company’s director of marketing and business development for integrated circuit design. Future tools could address X-specific issues, he says.

While Numerical Technology considers X Architecture “potentially revolutionary,” it looks forward to testing it out on actual chips, Sanie emphasizes. “Most of the things that have happened in the last 15 years, especially in EDA [electronic design automation] have been incremental stuff,” he says. “On paper, the concept looks very good.”

Missing from the X Files: Intel

X Architecture hasn’t received blessings from microprocessor heavyweights such as Advanced Micro Devices and Intel-although Intel is a Simplex investor. Teig expects Intel eventually to adopt X Architecture, but adds, “My expectation is they’ll lay back on it for a while.”

Intel sounds less sure. “It doesn’t provide much benefit in our processors,” says a spokesperson. “A regular ‘Manhattan’ array of interconnects will always be a more efficient way to use wires. Diagonal wires can be shorter in some cases and result in some speed-up, but this blocks the routing of other wires using the same layer, so you pay a significant interconnect density penalty for a limited performance gain.”

But X Architecture should succeed, if Simplex avoids the licensing battles that have hurt some promising design technologies in the past, predicts Gary Smith, an analyst at Gartner Dataquest in San Jose, CA. “As long as the technology holds up, and I fully expect it will, it is breakthrough technology,” Smith says.

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