New algorithms double flash capacity without shrinking transistor size.
Source: “A 5.6 MB/s 64 Gb 4b/Cell NAND Flash Memory in 43nm CMOS”
Cuong Trinh et al.
2009 IEEE International Solid-State Circuits Conference, February 10, 2009, San Francisco, CA
Results: Researchers at Toshiba and SanDisk, a maker of flash memory devices in Milpitas, CA, have built a 64-gigabit chip that holds four bits of data per memory cell, twice as much as the cells in conventional chips.
Why it matters: To increase the amount of data that can be stored in memory chips, engineers typically shrink the transistors that make up the individual memory cells. However, as transistors get smaller, their reliability tends to decrease because they generate more heat and leak more electrical current. While SanDisk researchers are still exploring ways to make transistors smaller without compromising reliability, the new approach makes it possible to store more data without shrinking transistors.
Methods: In conventional flash memory, a transistor stores two bits of data, each defined by a distinct voltage level. A variation of the technology can store four bits per transistor, but this requires more finely tuned voltage levels that can be disrupted by extreme voltage differences between transistors, effectively erasing the data. The SanDisk researchers wrote an algorithm that controls the way data is written to the chip so that the voltage differences between neighboring transistors are kept to a minimum.
Next steps: The company expects its chips to go into production within the first half of 2009. Future chips may use a similar principle, but since the electrical characteristics of transistors will change as smaller ones are developed, applying this approach to new generations of memory chips will require new algorithms that take these changes into account.