Extra Room for Transistors
New architecture could make chips faster and keep Moore’s Law alive
Source: “Nano/CMOS Architectures Using a Field-Programmable Nanowire Interconnect”
Gregory S. Snider and R. Stanley Williams
Nanotechnology 18: 035204
Results: Hewlett-Packard Labs researchers R. Stanley Williams and Greg Snider have redesigned the chips known as field-programmable gate arrays to make room for eight times as many transistors, without shrinking the transistors themselves.
Why it matters: As electronic devices, such as transistors, grow smaller, engineers can pack them closer together, producing faster and more powerful computer chips. In the next decade, however, the standard techniques for shrinking transistors will run up against fundamental physical limits, so engineers are looking for new ways to increase the density of chip circuitry.
Methods: In today’s chips, some of the silicon real estate is taken up by aluminum-wire interconnects that supply power and instructions to the transistors. To make room for more transistors, the HP researchers designed a chip whose wires are on top of instead of in between the transistors. They used what they called a “crossbar structure,” a sort of nanoscale wire mesh developed at HP. Each junction in the mesh acts as a switch that controls the flow of electrons to and from the transistor beneath it.
Next steps: The researchers are developing a laboratory prototype that uses the design, and Williams expects it to be complete by the end of the year. By 2010, he says, the technology should be ready for manufacturing.