The first huge barrier to bringing clockless chips to market is the lack of automated tools to accelerate their design. Twenty years ago, a handful of engineers could lay out a chip’s circuitry on paper. Today, hundreds of engineers work in teams, and the only hope of coordinating their actions is to use sophisticated computer-aided tools. But asynchronous designers face a chicken-and-egg problem: if there is no mass market for asynchronous chips, there’s little incentive to create tools to build them; if there are no tools, no chips get produced. The same problem applies to the development of chip-testing technologies. Without any significant quantity of asynchronous circuits to test, there is no market for third-party testing tools.In the case of its pager chips, Philips decided the only way out of this trap was to itself invest in developing the tools it needed. “After 13 years of research, we are now close to an effective and efficient test approach for asynchronous circuits,” says Philips research fellow Kees van Berkel, who has worked on the Dutch giant’s asynchronous team since the early 1980s. And Philips is not alone in this quest. In an effort to create momentum for asynchronous chips, two computer scientists-Steven Nowick at Columbia University and Steve Furber at the University of Manchester-have each developed design tools that they are giving away as shareware. “Tools are now the show stoppers,” says Nowick. “If you don’t have tools you can’t do things in portable ways, and you can’t train people to become experts.”
Beyond a new generation of design-and-testing equipment, successful development of clockless chips requires people who understand asynchronous design. Such talent is scarce, as asynchronous principles fly in the face of the way almost every university teaches its engineering students. Conventional chips can have values arrive at a register incorrectly and out of sequence; but in a clockless chip, the values that arrive in registers must be correct the first time. One way to achieve this goal is to pay close attention to such details as the lengths of the wires and the number of logic gates connected to a given register, thereby assuring that signals travel to the register in the proper logical sequence. But that means being far more meticulous about the physical design than synchronous designers have been trained to be.
An alternative, used by Theseus and others, is to open up a separate communication channel on the chip. Clocked chips represent ones and zeroes using low and high voltages on a single wire; “dual-rail” circuits, on the other hand, use two wires, giving the chip communications pathways, not only to send bits, but also to send “handshake” signals to indicate when work has been completed. Fant additionally proposes replacing the conventional system of digital logic with what he calls “null convention logic,” a scheme that identifies not only “yes” and “no,” but also “no answer yet”-a convenient way for clockless chips to recognize when an operation has not yet been completed. All of these ideas and approaches are different enough that executing them could confound the mind of an engineer trained to design to the beat of a clock. It’s no surprise that the two newest asynchronous startups, Asynchronous Digital Devices and Self-Timed Solutions, are populated by students coming out of Caltech and the University of Manchester, where clockless-chip research has been going on the longest.
For a chip to be successful, all three elements-design tools, manufacturing efficiency and experienced designers-need to come together. The asynchronous cadre has “very promising ideas,” says Max Baron, microprocessor analyst and editor of the industry newsletter Microprocessor Report. “But they don’t have the actual machine, and they haven’t proven they know how to build it.”
Though it will take far longer for clockless chips to go mainstream, we’re already seeing the beginnings of that transition as well. Intel, which shelved its asynchronous-chips project in 1997, incorporated elements of its clockless technology into the Pentium 4 chip that it released this year. “We’re introducing asynchronous design from the bottom up, designing in some pieces of unclocked logic in a chip that is still of conventional design,” says Stevens. “At this point, if we can do something asynchronously, and it’s better in terms of power consumption, then we will do it.”
So what of Karl Fant’s flamboyantly predicted revolution? In an industry as mature as chip making, there’s no replacing dictatorship with anarchy overnight. But over time, the balance will probably shift toward clockless design; enough articles will be written, enough tools built, enough engineers educated that it will no longer be unrealistic to imagine marketing such a chip even outside of specialized niches. “Once people understand how to do this easily, it will become more natural to think about asynchronous,” says Sun engineer Normoyle. “People won’t do it because it’s interesting. We’ll do it because it’s easier than something else. Our only goal is to be better than the other guys. The switch will come when synchronous is no longer good enough.”
The winners in this next wave of innovation will be the companies that choose the right time to jump off the curve. Clockless chips have the promise of revolutionizing the industry, of rapidly accelerating the relentless drive toward faster and cheaper chips that we’ve come to expect from Moore’s Law. Who is to say what might be possible? Why not an all-asynchronous chip compatible with Intel products?
“If someone does that, they will have a serious competitive advantage for a number of years,” says Intel’s Stevens. Translation? “So yeah, we’re worried.”
Let the anarchy begin.