Samsung's challenge, then, was to minimize the area that these windows take up by strategically distributing them, in much the same way that columns are used as structural supports in parking garages.

Another trick the researchers used, says Jung, was to simultaneously fabricate the wire interconnects used for communication between layers and beyond the chip. If the wires were added separately, the 3-D chips would be much more expensive to make, due to the extra steps involved in ensuring communication between layers.

Making the layers comparable in terms of performance was another challenge. Due to the electrical nature of the second layer (it's not grounded), only one memory cell can be erased at a time. In contrast, memory cells in the first layer can be erased in large chunks. In the researchers' prototype the second layer of memory cells initially took 32 times longer than the first to erase the same amount of data. Jung says the researchers overcame this challenge by designing a novel electrical scheme that grounds the second layer so that data can be erased in chunks and at the same speed as the first layer.

The prototype memory chip announced in San Francisco is still in its early stages and only has a capacity of 32 bits. Still, the results are encouraging. "I think it's an interesting demonstration of concept," says Subramanian. "The fact that they got it to work and they're getting very good electrical data, and the fact that the multiple layers built on top of each other work pretty nicely, is attractive."

Yet Subramanian cautions that the technology for 3-D flash still needs to prove its manufacturability. Even with Samsung's results, adding layers of silicon increases the number of steps in the process and ultimately makes the chip more expensive. "Flash memory is very driven by price, and it's a very cutthroat business," he says.

Bruce White, manager of advanced CMOS at Freescale Semiconductor, sees great promise in 3-D fabrication technologies for flash memory and beyond. "We see it as very important," he says. Not only could the capacity of solid-state storage increase significantly without taking up more chip real estate, but engineers could also mix and match solid-state devices to fit different applications. For instance, one layer could be flash, and another layer could be dynamic random-access memory, both fitting together like Lego blocks, White says. "We would like to be able to combine different technologies all on the same substrate."

Although Samsung didn't offer a specific timeline for its 3-D flash memory, Jung says that it could "be rapidly deployed because it can fully utilize existing 2-D planar technology."